From gc-linux

Contents 1 Introduction 2 Programming Interface 2.1 Register Access Protocol 2.1.1 Writing to a register 2.1.2 Reading from a register 2.2 Register dumps (from HBC) 2.2.1 PAL 480i 60Hz (composite) 2.2.2 PAL 576i 50Hz (composite) 2.2.3 NTSC 480p (component) 2.3 Register Dumps (from Zelda TP + Twilight Hack) 2.3.1 PAL 480i 60Hz (composite) 2.3.2 PAL 576i 50Hz (composite) 2.3.3 PAL 480i 60Hz (component) 2.3.4 PAL 576i 50Hz (component) 2.3.5 PAL 480p (component) 2.3.6 NTSC 480i (composite) 2.3.7 NTSC 480p (component) 2.3.8 NTSC 480i (component) 2.4 Register Descriptions 2.4.1 Register 00h 2.4.2 Register 01h 2.4.3 Register 02h 2.4.4 Register 03h 2.4.5 Register 04h 2.4.6 Registers 10h-31h 2.4.7 Registers 40h-5Ah 2.4.8 Register 62h 2.4.9 Register 65h 2.4.10 Register 67h 2.4.11 Register 6Ah 2.4.12 Register 6Dh 2.4.13 Register 6Eh

Introduction

The AVE-RVL is an audio/video encoder present on the Nintendo Wii video game console.

Programming Interface

The AVE-RVL encoder can be programmed via an I²C bus using its preconfigured slave address of 70h.

The I²C bus where the AVE-RVL sits can be accessed directly from the "Broadway" processor via two GPIO pins controllable through the memory mapped GPIO word found at 0x0d8000c{0,4,8} (bus address format). Bit 14 of that GPIO word is connected to the SCL line of the I²C bus, while bit 15 is connected to the SDA line of the same bus.

GPIO word at 0x0d8000c{0,4,8}

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
																SDA	SCL					disk eject	sensor bar			front led

The communication between the processor and the encoder follow the standard I²C specification.

The encoder can be programmed by writing configuration values to a set of registers.

Register Access Protocol

Writing to a register

• Start an I²C write transaction to address 70h
• Write a byte containing the address of the register you want to write to
• Write the contents of the register byte per byte, MSB first
• End the I²C transaction

Reading from a register

• Start an I²C write transaction to address 70h
• Write a byte containing the address of the register you want to read from
• Start an I²C read transaction to address 70h
• Read the contents of the register byte per byte, MSB first
• End the I²C transaction

Register dumps (from HBC)

These three dumps were generated using a helper kernel loaded with HBC on a PAL console. They reflect the initialization of AVE-RVL performed by libogc.

Note that HBC initializes 480p on a PAL console as if it was a NTSC console.

PAL 480i 60Hz (composite)

 yx!00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f
 --+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--
 00:00 02 07 01 01 00 00 FF 00 00 00 FF FF FF FF FF
 10:10 00 10 00 10 00 10 00 10 00 10 00 10 20 40 60
 20:80 A0 EB 10 00 20 00 40 00 60 00 80 00 A0 00 EB
 30:00 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
 40:FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
 50:FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
 60:FF FF 00 00 00 01 FF 00 00 FF 01 00 00 00 01 FF
 70:00 8E 8E FF FF FF FF FF FF FF 00 00 00 00 FF FF

Remarks:
Reg 01h = 02h
Reg 6eh = 01h

PAL 576i 50Hz (composite)

 yx!00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f
 --+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--
 00:00 02 07 01 01 00 00 FF 00 00 00 FF FF FF FF FF
 10:10 00 10 00 10 00 10 00 10 00 10 00 10 20 40 60
 20:80 A0 EB 10 00 20 00 40 00 60 00 80 00 A0 00 EB
 30:00 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
 40:FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
 50:FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
 60:FF FF 00 00 00 01 FF 00 00 FF 01 00 00 00 00 FF
 70:00 8E 8E FF FF FF FF FF FF FF 00 00 00 00 FF FF

Remarks:
Reg 01h = 02h
Reg 6eh = 00h

NTSC 480p (component)

 yx!00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f
 --+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--
 00:00 20 07 01 01 00 00 FF 00 00 00 FF FF FF FF FF
 10:10 00 10 00 10 00 10 00 10 00 10 00 10 20 40 60
 20:80 A0 EB 10 00 20 00 40 00 60 00 80 00 A0 00 EB
 30:00 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
 40:FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
 50:FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
 60:FF FF 00 00 00 01 FF 00 00 FF 01 00 00 00 00 FF
 70:00 8E 8E FF FF FF FF FF FF FF 00 00 00 00 FF FF

Remarks:
Reg 01h = 20h
Reg 6eh = 00h

Register Dumps (from Zelda TP + Twilight Hack)

These dumps were generated by loading a helper kernel using Zelda Twilight Princess and the Twilight Hack. As the Twilight Hack does not touch the AVE-RVL, these dumps reflect the initialization of the AVE-RVL performed by Zelda TP.

The PAL dumps were obtained from a PAL console. The NTSC dumps were obtained from a NTSC console.

PAL 480i 60Hz (composite)

 yx!00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f
 --+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--
 00:00 02 07 01 01 00 00 FF 00 00 00 FF FF FF FF FF
 10:10 00 10 00 10 00 10 00 10 00 10 00 10 20 40 60
 20:80 A0 EB 10 00 20 00 40 00 60 00 80 00 A0 00 EB
 30:00 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
 40:FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
 50:FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
 60:FF FF 00 00 00 01 FF 00 00 FF 01 00 00 00 01 FF
 70:00 8E 8E FF FF FF FF FF FF FF 00 00 00 00 FF FF

Remarks:
Reg 01h = 02h
Reg 6eh = 01h

PAL 576i 50Hz (composite)

 yx!00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f
 --+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--
 00:00 02 07 01 01 00 00 FF 00 00 00 FF FF FF FF FF
 10:10 00 10 00 10 00 10 00 10 00 10 00 10 20 40 60
 20:80 A0 EB 10 00 20 00 40 00 60 00 80 00 A0 00 EB
 30:00 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
 40:FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
 50:FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
 60:FF FF 00 00 00 01 FF 00 00 FF 01 00 00 00 00 FF
 70:00 8E 8E FF FF FF FF FF FF FF 00 00 00 00 FF FF

Remarks:
Reg 01h = 02h
Reg 6eh = 00h

PAL 480i 60Hz (component)

 yx!00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f
 --+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--
 00:00 22 07 01 01 00 00 FF 00 00 00 FF FF FF FF FF
 10:10 00 10 00 10 00 10 00 10 00 10 00 10 20 40 60
 20:80 A0 EB 10 00 20 00 40 00 60 00 80 00 A0 00 EB
 30:00 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
 40:FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
 50:FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
 60:FF FF 00 00 00 01 FF 00 00 FF 01 00 00 00 01 FF
 70:00 8E 8E FF FF FF FF FF FF FF 00 00 00 00 FF FF

Remarks:
Reg 01h = 22h
Reg 6eh = 01h

PAL 576i 50Hz (component)

 yx!00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f
 --+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--
 00:00 22 07 01 01 00 00 FF 00 00 00 FF FF FF FF FF
 10:10 00 10 00 10 00 10 00 10 00 10 00 10 20 40 60
 20:80 A0 EB 10 00 20 00 40 00 60 00 80 00 A0 00 EB
 30:00 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
 40:FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
 50:FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
 60:FF FF 00 00 00 01 FF 00 00 FF 01 00 00 00 00 FF
 70:00 8E 8E FF FF FF FF FF FF FF 00 00 00 00 FF FF

Remarks:
Reg 01h = 22h
Reg 6eh = 00h

PAL 480p (component)

 yx!00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f
 --+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--
 00:00 22 07 01 01 00 00 FF 00 00 00 FF FF FF FF FF
 10:10 00 10 00 10 00 10 00 10 00 10 00 10 20 40 60
 20:80 A0 EB 10 00 20 00 40 00 60 00 80 00 A0 00 EB
 30:00 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
 40:FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
 50:FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
 60:FF FF 00 00 00 01 FF 00 00 FF 01 00 00 00 01 FF
 70:00 8E 8E FF FF FF FF FF FF FF 00 00 00 00 FF FF

Remarks:
Reg 01h = 22h
Reg 6eh = 01h

NTSC 480i (composite)

 yx!00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f
 --+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--
 00:00 00 07 01 01 00 00 FF 00 00 00 FF FF FF FF FF
 10:10 00 10 00 10 00 10 00 10 00 10 00 10 20 40 60
 20:80 A0 EB 10 00 20 00 40 00 60 00 80 00 A0 00 EB
 30:00 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
 40:FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
 50:FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
 60:FF FF 00 00 00 01 FF 00 00 FF 01 00 00 00 00 FF
 70:00 8E 8E FF FF FF FF FF FF FF 00 00 00 00 FF FF

Remarks:
Reg 01h = 00h
Reg 6eh = 00h

NTSC 480p (component)

 yx!00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f
 --+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--
 00:00 20 07 01 01 00 00 FF 00 00 00 FF FF FF FF FF
 10:10 00 10 00 10 00 10 00 10 00 10 00 10 20 40 60
 20:80 A0 EB 10 00 20 00 40 00 60 00 80 00 A0 00 EB
 30:00 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
 40:FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
 50:FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
 60:FF FF 00 00 00 01 FF 00 00 FF 01 00 00 00 00 FF
 70:00 8E 8E FF FF FF FF FF FF FF 00 00 00 00 FF FF

Remarks:
Reg 01h = 20h
Reg 6eh = 00h

NTSC 480i (component)

 yx!00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f
 --+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--
 00:00 20 07 01 01 00 00 FF 00 00 00 FF FF FF FF FF
 10:10 00 10 00 10 00 10 00 10 00 10 00 10 20 40 60
 20:80 A0 EB 10 00 20 00 40 00 60 00 80 00 A0 00 EB
 30:00 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
 40:FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
 50:FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
 60:FF FF 00 00 00 01 FF 00 00 FF 01 00 00 00 00 FF
 70:00 8E 8E FF FF FF FF FF FF FF 00 00 00 00 FF FF

Remarks:
Reg 01h = 20h
Reg 6eh = 00h

Register Descriptions

Register 00h

Unknown. Default value is 0.

Register description

address	size	read/write	description
00h	1	W	unknown

Register 01h

Register description

address	size	read/write	description
01h	1	W	video format control

Register bit definitions

bit(s)	name	description
0		?? 1=video off
1		1=PAL 0=NTSC
5		1=component video output (RVL-011) 0=non-component video output (RVL-009, RVL-013, ...)

Register 02h

Unknown. Default value is 7.

Register description

address	size	read/write	description
02h	1	W	unknown

Register 03h

Unknown. Default value is 1.

Register description

address	size	read/write	description
03h	1	W	unknown

Register 04h

Unknown. Default value is 1.

Register description

address	size	read/write	description
04h	1	W	unknown

Registers 10h-31h

These registers store gamma correction values.

Registers 40h-5Ah

These registers store macrovision related information.

Register 62h

Register description

address	size	read/write	description
62h	1	W	control

Register bit definitions

bit(s)	name	description
1		1=swap blue and red signals 0=normal behaviour

Register 65h

Unknown. Default value is 1.

Register description

address	size	read/write	description
65h	1	W	unknown

Register 67h

Register description

address	size	read/write	description
67h	1	W	control

Register bit definitions

bit(s)	name	description
1		1=show color test pattern display 0=show normal display

Register 6Ah

Unknown. Default value is 1.

Register description

address	size	read/write	description
6Ah	1	W	unknown

Register 6Dh

Register description

address	size	read/write	description
6Dh	1	W	control

Register bit definitions

bit(s)	name	description
4		1=switch off audio 0=switch on audio

Register 6Eh

Unknown. Default value is 0 or 1, depending on video mode.

Register description

address	size	read/write	description
6Eh	1	W	unknown

Register bit definitions

bit(s)	name	description
0		1=PAL 525-lines 0=otherwise